A MOSFET has been developed that breaks a conventional characteristic limit, using a super-junction structure in which p-type and n-type regions are arranged in parallel, alternating in position in a plane parallel to the primary plane of a semiconductor substrate. One method of forming this super-junction structure is by a multi-step epi system, a structure where an epi layer is incrementally grown so that plural p-type and n-type regions called laminar layers, reeds, or columns (pillars), which extend in a direction perpendicular to the primary plane of the semiconductor substrate are formed to be arranged alternating in position and in parallel along the direction of the plane parallel to the primary plane of the semiconductor substrate (this structure will hereinafter be referred to as pn column structure or simply as column structure) by ion implantation using a mask. “epi” is an abbreviation of epitaxial, which may be abbreviated as “epi” hereinafter.
A trench implant epi system is a method of forming the pn column structure described above by forming plural trenches of a high aspect ratio on the n-type epi substrate and implanting the p-type silicon by epitaxial growth into these trenches. As compared with the MOSFET of an ordinary junction structure, the pn column structure formed by either system is excellent in that the tradeoff between on-resistance and withstanding voltage characteristics may be improved, since a high withstanding voltage is attainable even when using p and n columns of low resistivity.
When a surface pattern of the p and n columns forming the super-junction structure, as viewed from above the wafer, has a stripe pattern in a longitudinal direction, as depicted in FIG. 3, which is a partial, cross-sectional perspective diagram of the conventional super-junction (SJ-) MOSFET, it is preferable that, in light of device characteristics, a MOS cell stripe pattern in the longitudinal direction be parallel to the stripe pattern of the super-junction structure. When the two stripes are orthogonal, as depicted in FIG. 4, which is a partial, cross-sectional perspective diagram, a current path in the vicinity of the surface is twisted, increasing the on-resistance. If the two stripes are parallel, the problem of twisted current paths does not occur and low on-resistance is maintained.
At the time of switching operation of the MOSFET, parasitic capacity components, namely, gate-source capacity Cgs, drain-source capacity Cds, and gate-drain capacity Cgd, significantly affect switching waveform. In particular, when the gate-drain capacity Cgd is too large, Miller capacity increases, switching becomes slow, and switching loss increases. On the other hand, when the gate-drain capacity Cgd is too small, the switching loss becomes small but the rate of rise of the drain-source voltage Vds at the time of turn-off becomes too large, causing radiation noise and adversely affecting external apparatuses. Therefore, design of a structure to bring the gate-drain capacity Cgd to an appropriate value is very important for the switching characteristics.
Further, description has been disclosed for a super-junction-structure semiconductor device having a structure where the p column layer is connected by a p-type intermediate region (see, e.g., Patent Documents 1 and 2 below).